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? semiconductor components industries, llc, 2005 december, 2005 ? rev. 4 1 publication order number: ncp1601a/d ncp1601a, NCP1601B compact fixed frequency discontinuous or critical conduction voltage mode power factor correction controller the ncp1601 is a controller designed for power factor correction (pfc) boost circuits. the device operates in fixed?frequency discontinuous conduction mode (dcm) and variable?frequency critical conduction mode (crm) and takes advantages from both operating modes. dcm limits the maximum switching frequency. it simplifies the front?ended emi filter design. crm limits the maximum currents of the boost stage diode, mosfet and inductor. it reduces the costs and improves the reliability of the circuit. this device substantially exhibits unity power factor while operating in dcm and crm. the ncp1601 minimizes the required number of external components. it incorporates high safety protection features that make the ncp1601 suitable for robust and compact pfc stages. features ? near?unity power factor in dcm or crm ? voltage?mode operation ? low startup and shutdown current consumption ? programmable switching frequency for dcm ? synchronization capability ? overvoltage protection (107% of nominal output level) ? undervoltage protection or shutdown (8% of nominal output level) ? programmable overcurrent protection ? thermal shutdown with hysteresis (95/140 c) ? two v cc undervoltage lockout hysteresis options: 4.75 v for ncp1601a and 1.5 v for NCP1601B ? pb?free packages are available typical applications ? electronic light ballast ? ac adapters ? tv & monitors ? mid?power applications marking diagram x = a or b a = assembly location l, wl = wafer lot y, yy = year w, ww = work week = pb?free package g = pb?free package http://onsemi.com pdip?8 n suffix case 626 1 8 1 8 soic?8 d suffix case 751 ncp1601x awl yywwg 1 8 1601x alyw 1 8 pin connections 1 fb 8 v cc 2 v control 3 ramp 4 cs 7 drv 6 gnd 5 osc (top view) see detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ordering information
ncp1601a, NCP1601B http://onsemi.com 2 ac input emi filter output ramp gnd v control drv fb v cc cs osc 15 v ncp1601x figure 1. typical application circuit figure 2. functional block diagram fb ref reg v i i 96% ? + + ? + ? ? + & & 1 8 4 5 2 3 7 6 & ac input emi filter c filter l r cs i s off on c bulk r fb output voltage (v out ) i fb r s cs fb / sd c control v control 9 v 9 v 18 v v cc(on) / 9 v v cc v cc 300 k current mirror vcontrol processing uvlo v cc regulation block current mirror 3.9 vmax clamp internal bias reference block ref i overvoltage protection (i fb > 107% i ref ) overcurrent protection (i s > 203 a) zero current detection (i s < 14 a) shutdown / uvp (i fb < 8% i ref ) pfc modulation r 1 r 2 r 3 c 3 c 1 thermal shutdown (95 / 140 c) 01 v ton i ch c ramp ramp 9 v 9 v v cc 9 v 0 1 45 a 94 a c osc osc / sync 01 oscillator / synchronization block output driver drv gnd delay 5 / 3.5 v s r q s r q or
ncp1601a, NCP1601B http://onsemi.com 3 pin function description pin symbol function function 1 fb feedback / shutdown this pin receives a current i fb which is proportional to the pfc circuit output voltage. the current is for the output regulation, output overvoltage protection (ovp), and output undervoltage protection (uvp). when i fb goes above 107% i ref , ovp is activated and the drive output is disabled. when i fb goes below 8% i ref , the device enters a low?current consumption shutdown mode. 2 v control control the voltage of this pin v control directly controls the input impedance and hence the power factor of the circuit. this pin is connected to an external capacitor to limit the control voltage v control band- width typically below 20 hz to achieve power factor correction. 3 ramp ramp this pin is connected to an external capacitor to set a ramp signal. the capacitor value directly affects the input impedance of the pfc circuit and hence the maximum input power. 4 cs current sense this pin sources a current i s which depends on the inductor current and an offset voltage. the current is for overcurrent protection (ocp) and zero current detection. when i s is above 200 a, ocp is activated and the drive output is disabled. when i s is below 14 a, the circuit detects a zero current. this information is used by the on?time modulation arrangement and by the oscillator block. 5 osc oscillator / synchronization in oscillator mode, this pin is connected to an external capacitor to set the oscillator frequency of the dcm operation. in synchronization mode, this pin is connected to an external driving signal. the positive edge of the drive output is synchronized to the negative edge of the external signal in dcm operation. if the inductor current is non?zero at the end of a switching period, the output drive is not allowed to turn on. ccm operation is prohibited. instead, the circuit operates in crm in this case. 6 gnd the ic ground ? 7 drv drive output this pin provides an output to an external mosfet. 8 v cc supply v oltage this pin is the positive supply of the device. the operating range is between 9 v and 18 v with uvlo start threshold 13.75 v for ncp1601a and 10.5 v for NCP1601B. maximum ratings rating symbol value unit fb, v control , ramp, cs, osc pins (pins 1?5) maximum voltage range maximum current v max i max ?0.3 to +9 100 v ma drive output (pin 7) maximum voltage range maximum current range (note 2) v max i max ?0.3 to +18 ?500 to +750 v ma power supply voltage (pin 8) maximum voltage range maximum current v max i max ?0.3 to +18 100 v ma power dissipation and thermal characteristics p suffix, plastic package, case 626 maximum power dissipation @ t a =70 c thermal resistance, junction?to?air d suffix, plastic package, case 751 maximum power dissipation @ t a =70 c thermal resistance, junction?to?air p d r ja p d r ja 800 100 450 178 mw c/w mw c/w operating junction temperature range t j ?40 to +125 c storage temperature range t stg ?65 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limi t values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be af fected. a. this device series contains esd protection and exceeds the following tests: pins 1?8: human body model 2000 v per mil?std?883, method 3015. machine model method 200 v. b. this device contains latchup protection and exceeds 100 ma per jedec standard jesd78. 1. guaranteed by design.
ncp1601a, NCP1601B http://onsemi.com 4 electrical characteristics (for typical values t j = 25 c. for min/max values, t j = ?40 c to +125 c, v cc = 15 v, v control = 100 nf, ramp = 100 pf, osc = 220 pf unless otherwise specified) characteristic pin symbol min typ max unit oscillator oscillator frequency (osc = 220 pf to gnd) 5 f osc 52 58 64 khz internal capacitance of the oscillator pin 5 c osc(int) ? 36 ? pf maximum oscillator switching frequency 5 f osc(max) ? 405 ? khz oscillator discharge current (osc = 5.5 v) 5 i odch 40 49 60 a oscillator charge current (osc = 3 v) 5 i och 40 45 60 a comparator lower threshold (osc = 220 pf to gnd) (note 3) 5 v sync(l) 3.0 3.5 4.0 v comparator upper threshold (osc = 220 pf to gnd) 5 v sync(h) 4.5 5 5.5 v synchronization pulse width for detection 5 t sync(min) 500 ? ? ns synchronization propagation delay 5 t sync(d) ? 371 ? ns gate drive gate drive resistor output high and draw 100 ma out of drv pin (i source = 100 ma) output low and insert 100 ma into drv pin (i sink = 100 ma) 7 r oh r ol 5 2 11.6 7.2 20 18 gate drive rise time from 1.5 v to 13.5 v (drv = 1 nf to gnd) 7 t r ? 53 ? ns gate drive fall time from 13.5 v to 1.5 v (drv = 1 nf to gnd) 7 t f ? 32 ? ns feedback / overvoltage protection / undervoltage protection reference current 1 i ref 192 203 208 a regulation block ratio 1 i regl / i ref 95 96 97 % v control pin internal resistor 2 r control ? 300 ? k maximum control voltage (i fb = 100 a) 2 v control(max) 0.95 1.05 1.15 v feedback pin voltage (i fb = 100 a) 1 v fb1 ? 3 ? v overvoltage protection current ratio 1 i ovp / i ref 104 107 ? % overvoltage protection current 1 i ovp ? 217 225 a undervoltage protection current ratio 1 i uvp / i ref 4 8 15 % current sense current sense pin offset voltage (i s = 100 a) 4 v s ? 4 ? mv overcurrent protection level 4 i s(ocp) 190 203 210 a current sense pin offset voltage at overcurrent level 4 v s(ocp) 0 3.2 20 mv zero current detection level 4 i s(zcd) 9 14 19 a current sense pin offset voltage at zero current level 4 v s(zcd) 0 7.5 20 mv zero current sense resistor (r s(zcd) = v s(zcd) / i s(zcd) ) 4 r s(zcd) ? 0.536 1 k ramp charging current (ramp = 0 v) 3 i ch 95 100 105 a maximum power resistance (r power = v control(max) / i ch ) 3 r power 9.5 10.5 11.5 k internal clamping of voltage v ton ? v ton(max) ? 3.9 ? v internal capacitance of the ramp pin 3 c ramp(int) ? 20 ? pf ramp pin sink resistance (osc = 0 v, ramp = 1 ma sourcing) 3 r ramp ? 71.5 ? thermal shutdown thermal shutdown threshold (note 4) ? t sd 140 ? ? c thermal shutdown hysteresis ? t h ? 45 ? c 2. comparator lower threshold is also the synchronization threshold. 3. guaranteed by design.
ncp1601a, NCP1601B http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c. for min/max values, t j = ?40 c to +125 c, v cc = 15 v, v control = 100 nf, ramp = 100 pf, osc = 220 pf unless otherwise specified) characteristic unit max typ min symbol pin supply section startup threshold (uvlo) ? ncp1601a startup threshold (uvlo) ? NCP1601B 8 v cc(on) 12.5 9.6 13.75 10.5 15 11.4 v v minimum voltage for operation after t urn?on 8 v cc(off) 8.25 9 9.75 v uvlo hysteresis ? ncp1601a uvlo hysteresis ? NCP1601B 8 v cc(h) 4 1 4.75 1.5 ? ? v v power supply current: startup (v cc = v cc(on) ? 0.2 v) operating (v cc = 15 v, drv = open, osc = 220 pf) operating (v cc = 15 v, drv = 1 nf to gnd, osc = 220 pf) shutdown (v cc = 15 v, i fb = 0 a) 8 i stup i cc1 i cc2 i stdn ? ? ? ? 17 2.7 3.7 24 40 5 5 50 a ma ma a typical characteristics f osc , oscillator frequency (khz) figure 3. oscillator frequency vs. temperature t j , junction temperature ( c) 50 51 52 53 54 55 56 ?50 0 25 50 75 100 125 figure 4. oscillator charge and discharge current vs. temperature figure 5. oscillator comparator thresholds vs. temperature figure 6. drive output resistance vs. temperature ?25 57 58 59 60 oscillator charge & discharge current ( a) t j , junction temperature ( c) 44 45 46 47 48 49 50 ?50 0 25 50 75 100 125 ?25 51 c osc = 220 pf i odch osc pin = 5.5 v i och osc pin = 3 v oscillator comparator thresholds (v) t j , junction temperature ( c) 3 3.5 4.0 4.5 ?50 0 25 50 75 100 125 ?25 5.0 5.5 gate drive resistance ( ) t j , junction temperature ( c) 0 2 4 6 8 10 12 ?50 0 25 50 75 100 125 ?25 14 c osc = 220 pf r oh v sync(h) v sync(l) 16 18 r ol
ncp1601a, NCP1601B http://onsemi.com 6 typical characteristics regulation block ratio (%) t j , junction temperature ( c) 90 91 92 93 94 95 96 ?50 0 25 50 75 100 125 ?25 97 98 99 100 maximum control voltage (v) t j , junction temperature ( c) 1.00 1.02 1.04 1.06 1.08 1.10 ?50 0 25 50 75 100 12 5 ?25 i fb = 100 a feedback pin voltage (v) i fb , feedback pin current ( a) 2 3 4 5 50 100 150 200 250 0 6 overvoltage protection ratio (%) t j , junction temperature ( c) 105 105.5 106 106.5 107 107.5 108 ?50 0 25 50 75 100 12 5 ?25 108.5 109 110 t j = 25 c 0 1 109.5 t j = ?40 c t j = 125 c v control , control voltage (v) figure 7. reference current vs. temperature figure 8. regulation block transfer function 0 0.2 0.4 0.6 0.8 1.2 150 160 170 180 190 200 22 0 i fb , feedback current ( a) i ref , reference current ( a) t j , junction temperature ( c) 194 196 198 200 202 204 206 ?50 0 25 50 75 100 125 ?25 t j = 25 c 1.0 210 t j = 125 c t j = ?40 c 208 210 190 192 figure 9. regulation block ratio vs. temperature figure 10. maximum control voltage vs. temperature figure 11. feedback pin voltage vs. feedback current figure 12. overvoltage protection ratio vs. temperature
ncp1601a, NCP1601B http://onsemi.com 7 typical characteristics cs pin offset voltage (mv) i s , cs pin current ( a) 0 20 40 60 80 100 120 0 100 150 200 250 50 cs pin offset voltage (mv) t j , junction temperature ( c) 0 1 2 3 4 5 6 ?50 0 25 50 75 100 125 ?25 7 t j = ?40 c v s(zcd) v s(ocp) overcurrent protection level ( a) t j , junction temperature ( c) ?50 0 25 50 75 100 125 ?25 zero current detection level ( a) t j , junction temperature ( c) 10.0 10.5 11.0 11.5 12.0 12.5 13.0 ?50 0 25 50 75 100 125 ?25 13.5 14.0 15.0 8 9 10 190 192 194 196 198 200 202 204 206 210 14.5 t j = 25 c t j = 125 c 208 figure 13. overvoltage protection threshold vs. temperature figure 14. undervoltage protection ratio vs. temperature overvoltage threshold ( a) t j , junction temperature ( c) 208 210 212 214 216 218 220 ?50 0 25 50 75 100 125 ?25 undervoltage protection ratio (%) t j , junction temperature ( c) 0 1 2 3 4 5 6 ?50 0 25 50 75 100 125 ?25 7 8 10 9 200 202 204 206 figure 15. cs pin offset voltage vs. current figure 16. cs pin offset voltage at ocp, zcd vs. temperature figure 17. overcurrent protection level vs. temperature figure 18. zero current detection level vs. temperature
ncp1601a, NCP1601B http://onsemi.com 8 typical characteristics maximum power resistance (k ) t j , junction temperature ( c) 9.0 10.0 11.0 12.0 ?50 0 25 50 75 100 125 ?25 v cc undervoltage lockout thresholds (v) t j , junction temperature ( c) 8 9 10 11 12 13 15 ?50 0 25 50 75 100 12 5 ?25 v cc = 15 v, c osc = 220 pf i stdn v cc(off) i stup v cc supply current in startup and shutdown mode ( a) t j , junction temperature ( c) 0 5 10 15 20 25 35 ?50 0 25 50 75 100 125 ?25 v cc supply current with 1.0 nf load and without load (ma) t j , junction temperature ( c) 2 2.2 2.4 2.6 2.8 3 3.2 ?50 0 25 50 75 100 12 5 ?25 9.5 10.5 11.5 30 3.4 3.6 3.8 4 i cc2 , 1 nf load i cc1 , no load figure 19. zero current sense resistor vs. temperature figure 20. charging current vs. temperature zero current sense resistor ( ) t j , junction temperature ( c) 0 100 200 300 400 500 700 ?50 0 25 50 75 100 125 ?25 i ch , charging current ( a) t j , junction temperature ( c) 95 96 97 98 99 100 102 ?50 0 25 50 75 100 12 5 ?25 600 101 103 105 104 figure 21. maximum power resistance vs. temperature figure 22. supply voltage undervoltage lockout thresholds vs. temperature figure 23. supply current in startup and shutdown mode vs. temperature figure 24. supply current vs. temperature 14 v cc(on) for ncp1601a v cc(on) for NCP1601B
ncp1601a, NCP1601B http://onsemi.com 9 functional description introduction the ncp1601 is a power factor correction (pfc) boost controller designed to operate in discontinuous conduction mode (dcm) and critical conduction mode (crm). the fixed?frequency nature of dcm limits the maximum switching frequency. it limits the possible conducted and radiated emi noise that may pollute surrounding systems. ncp1601 offers the simplest solution to pfc including fewer external circuit components and simple voltage?mode feedback. the diode turn?off switching loss is negligible and hence there is no need to use a low reverse?recovery time t rr diode. on the other hand, the crm feature is added to limit the maximum current stress to twice of the average current. the ncp1601 incorporates high safety protection features and combines the advantages of dcm and crm so that the ncp1601 is suitable for robust and compact pfc stages. the ncp1601 provides the following protection features: 1. overvoltage protection (ovp) is activated and the output drive goes low when the output voltage exceeds 107% of the nominal regulation level which is a user?defined value. the circuit automatically resumes operation when the output voltage becomes lower than 107%. 2. undervoltage protection (uvp) is activated and the device is shut down when the output voltage goes below 8% of the nominal regulation level. the circuit automatically resumes operation when the output voltage goes above 8% of the nominal regulation level. this feature also provides output open?loop protection and external shutdown feature. 3. overcurrent protection (ocp) is activated and the output device goes low when the inductor current exceeds a user?defined value. the operation automatically resumes when the inductor current becomes lower than this user?defined value at the next clock cycle. 4. thermal shutdown (tsd) is activated and the output drive is disabled when the junction temperature exceeds 140 c. the operation resumes when the junction temperature falls down by typical 45 c. the ncp1601 is available in two versions. the ncp1601a has a typical 4.75 v undervoltage lockout (uvlo) hysteresis, while NCP1601B has a typical 1.5 v uvlo hysteresis. it allows the use of dif ferent v cc biasing schemes. operating modes of ncp1601 the ncp1601 is a pfc driver primarily designed to operate in fixed?frequency dcm. in the most stressful conditions, crm can be an alternative option which is without power factor degradation. on the other hand, the ncp1601 can be viewed as a crm controller with a frequency clamp (maximum switching frequency limit) alternative option which is also without power factor degradation. in summary, the ncp1601 can cover both crm and dcm without power factor degradation. based on the selections of the boost inductor and the oscillator frequency, the circuit is capable of the following three applications. 1. ?mostly in crm? with a frequency clamp set by the oscillator or synchronization frequency. 2. ?mostly in fixed?frequency mode dcm? and only run in crm at high load and low line. 3. ?fixed?frequency dcm? only. figure 25. operating modes inductor current, i l input current, i in time current dcm dcm critical mode dcm needs higher peak inductor current comparing to crm in the same averaged input current. hence, crm is generally preferred at around the sinusoidal peak for lower the maximum current stress but dcm is also preferred at the non?peak region to avoid excessive switching frequencies. because of the variable?frequency feature of the crm and constant?frequency feature of dcm, switching frequency is the maximum in the dcm region and hence the minimum switching frequency will be found at the moment of the sinusoidal peak. dcm pfc circuit a dcm/crm pfc boost converter is shown in figure 26. input voltage is a rectified 50 or 60 hz sinusoidal signal. the mosfet is switching at a high frequency (typically around 100 khz) so that the inductor current i l basically consists of high?frequency and low?frequency components. filter capacitor c filter is an essential and very small value capacitor in order to eliminate the high?frequency content of the dcm inductor current i l . this filter capacitor cannot
ncp1601a, NCP1601B http://onsemi.com 10 be too bulky because it can pollute the power factor by distorting the rectified sinusoidal input voltage. figure 26. dcm/crm pfc boost converter v in i in i l l v out c bulk c filter pfc methodology ncp1601 uses a proprietary pfc methodology particularly designed for both dcm and crm operation. the pfc methodology is described in this section. figure 27. inductor current in dcm t 1 t 2 t 3 i pk t tim e inductor current as shown in figure 27, the inductor current i l of each switching cycle starts from zero in dcm. crm is a special case of dcm when t 3 = 0. when the pfc boost converter mosfet is on, the inductor current i l increases from zero to i pk for a time duration t 1 with inductance l and input voltage v in . (eq.1) is formulated. v in l i pk t 1 (eq.1) the input filter capacitor c filter and the front?ended emi filter absorb the high?frequency component of inductor current. it makes the input current i in a low?frequency signal. i in i pk ( t 1 t 2 ) 2t (eq.2a) for dcm i in i pk 2 (eq.2b) for crm from (eq.1) and (eq.2), the input impedance z in is formulated. z in v in i in 2tl t 1 ( t 1 t 2 ) (eq.3a) for dcm z in v in i in 2l t 1 (eq.3b) for crm power factor is corrected when the input impedance z in in (eq.3) are constant or slowly varying. the mosfet on time t 1 or pfc modulation duty is generated by a feedback signal v ton and a ramp. the pfc modulation circuit and timing diagram are shown in figure 28. a relationship in (eq.4) is obtained. t 1 c ramp v ton i ch (eq.4) figure 28. pfc modulation circuit and timing diagram ? + closed when output low pfc modulation turns off mosfet ramp 3 c ramp i ch v ton v ton ramp output the charging current i ch is constant 100 a current and the ramp capacitor c ramp is constant for a particular design. hence, according to (eq.4) the mosfet on time t 1 is proportional to v ton . in order to protect the pfc modulation comparator, the maximum voltage of v ton is limited to internal clamp v ton(max) (3.9 v typical) and the ramp pin (pin 3) is with a 9 v esd zener diode. the 3.9 v maximum limit of this v ton indirectly limits the maximum on time. figure 29. v control processing circuit + ? closed when zero current 2 c control v control r 1 r 2 r 3 c 1 c 3 v ton the v control processing circuit generates v ton from control voltage v control and time information of zero inductor current. the circuit in figure 29 makes (eq.5) where the value of resistor r 1 is much higher than the value of resistor r 2 (r 1 >> r 2 ). v ton tv control t 1 t 2 (eq.5a) for dcm
ncp1601a, NCP1601B http://onsemi.com 11 v ton v control (eq.5b) for crm it is noted that v ton is always greater than or equal to v control (i.e., v ton v control ). in summary, the input impedance z in in (eq.6) is obtained from (eq.1)?(eq.5) z in v in i in 2li ch c ramp v control (eq.6) control voltage v control comes from the pfc output voltage v out which is a slowly varying signal. the bandwidth of v control can be additionally limited by inserting an external capacitor c control to the v control pin (pin 2) in figure 28. the internal 300 k resistor and the capacitor c control create a low?pass filter which has a bandwidth f control in (eq.7). it is generally recommended to limit the bandwidth below 20 hz to achieve power factor correction. typical value of c control is 0.1 f. c control 1 2 300k f control (eq.7) if the bandwidth of v control is much less than the 50 or 60 hz line frequency, the input impedance z in is slowly varying or roughly constant. then, the power factor correction is achieved in dcm and crm. figure 30. v control low?pass filtering 300k regulation block 2 c control v control v reg i ref i ref 96% i fb v control processing circuit maximum power input and output power (p in and p out ) are derived in (eq.8) when the circuit efficiency is obtained or assumed. the variable v ac stands for the rms input voltage. (eq.8a) p in v ac 2 z in v ac 2 c ramp v control 2li ch (eq.8b) p out p in v ac 2 c ramp v control 2li ch from (eq.8), control voltage v control controls the amount of output power, input power, or input impedance. the maximum value of the control voltage v control is 1.05 v (i.e., v control(max) = 1.05 v). a parameter called maximum power resistor r power (10.5 k typical) is defined in (eq.9) and restricted to have a maximum 10% variation (i.e., 9.5 k r power 11.5 k ) for defining the maximum power in an application. r power v control(max) i ch 1.05 v 100 a 10.5 k (eq.9) it means that the maximum input and output power (p in(max) and p out(max) ) are limited to 10% variation. (eq.10a) p in(max) v ac 2 c ramp r power 2l (eq.10b) p out(max) v ac 2 c ramp r power 2l the maximum input current i ac(max) to deliver the maximum input power p in(max) is also derived in (eq.11). the suffix ac stands for rms value. (eq.11) i ac(max) p in(max) v ac v acc ramp r power 2l output feedback the output voltage v out of the pfc circuit is sensed as a feedback current i fb flowing into the fb pin (pin 1) of the device. the fb pin voltage v fb1 is typically less than 5 v referring to figure 11. it is much lower than v out which is typically 400 v. therefore, v fb1 is generally neglected. (eq.12) i fb v out v fb1 r fb v out r fb where r fb is the feedback resistor connected between the fb pin (pin 1) and the output voltage referring to figure 2. then, the feedback current i fb represents the output voltage v out and will be used in the output voltage regulation, undervoltage protection (uvp), and overvoltage protection (ovp). output voltage regulation feedback current i fb , which presents output voltage v out , is regulated with a reference current (i ref = 203 a typical) as shown in figure 31. figure 31. regulation block v reg i ref i ref 96% i fb 1.05 v when i fb is lower than 96% of i ref , the v reg which is the output of the regulation block is as high as v control(max) (1.05 v typical) that gives the maximum value on v ton . as a result, it gives the maximum mosfet on time and v out increases. when i fb is higher than i ref , the v reg becomes 0 v that gives no mosfet on time and v out decreases. as a result, the output voltage v out is regulated around the range between 96% and 100% of the nominal value of r fb i ref . based on (eq.8) for a particular power level, the v control is inversely proportional to v ac 2 . hence, in high v ac condition v control is lower. it means that i fb or output
ncp1601a, NCP1601B http://onsemi.com 12 voltage is higher based on the regulation block characteristic in figure 31. on the other hand, the v control in the low v ac condition is much higher than the high v ac condition. in order to not over?design the circuit in the application, the v control in the low v ac condition is usually very closed to v control(max) . it makes the output voltage be almost 96% of the nominal value of r fb i ref in low v ac condition while the output voltage is almost 100% of the nominal value r fb i ref in high v ac condition. the feedback resistor r fb consists of two or three high precision resistors in order to set the nominal v out precisely and safety purpose. the regulation block output v reg is connected to control voltage v control through an internal resistor r control (300 k typical) for the low?pass filter in figure 30. the v control and the time information of zero current are collected in the v control processing circuit to generate v ton which is then compared to a ramp signal to generate the mosfet on time t 1 for power factor correction. overvoltage protection (ovp) when the feedback current i fb is higher than 107% of the reference current i ref (i.e., the output voltage v out is higher than 107% of its nominal value), the drive output pin (pin 7) of the device goes low for protection and the switch of the v control processing circuit is kept off. the circuit automatically resumes operation when the output voltage is lower than 107%. the maximum ovp threshold is limited to 225 a which corresponds to 225 a 1.95 m + 5 v = 443.75 v when r fb = 1.95 m (1.8 m + 150 k ) and v fb1 = 5 v (for the worst case referring to figure 11). hence, it is generally recommended to use 450 v rating output capacitor to allow some design margin. undervoltage protection (uvp) when the feedback current i fb is lower than 8% of the reference current i ref (i.e., the output voltage v out is lower than 8% of its nominal value), the device is shut down and consumes lower than 50 a. in normal situation of boost converter configuration, the output voltage v out is always higher than the input voltage v in and the feedback current i fb is always higher than 8% of the reference current i ref . it enables the ncp1601 to operate. hence, uvp happens when the output voltage is abnormally undervoltage, the fb pin (pin 1) is opened, or the fb pin (pin 1) is manually pulled low. current sense the device senses the inductor current i l by the current sense scheme in figure 32. this scheme has the advantages of: (1) the inrush current limitation by the resistor r cs , and (2) the overcurrent protection and zero current detection implemented in the same pin. figure 32. current sensing cs ncp1601 gnd + ? r cs r s i l i s i l v s inductor current i l passes through r cs and creates a negative voltage. this voltage is measured by a current i s flowing out of the cs pin (pin 4). the cs pin has an offset voltage v s . this offset voltage is studied in the setting of zero inductor current i l(zcd) and the maximum inductor current i l(ocp) (i.e., overcurrent protection threshold). a typical variation of offset voltage v s versus sense current i s is shown in figure 15. higher the value of the offset voltage at low current region creates lower the zero current threshold for better accuracy. based on figure 32, (eq.13) is derived. (eq.13) v s r s i s ?r cs i l zero current detection (zcd) the device recognizes zero inductor current when the cs pin (pin 4) sense current i s is lower than i s(zcd) (14 a typical). the offset voltage of the cs pin in this condition is v s(zcd) (7.5 mv typical). it is illustrated in figure 33. the inductor current i l(zcd) at the zcd condition is derived in (eq.14). (eq.14) i l(zcd) r s i s(zcd) v s(zcd) r cs it is obvious that the i l(zcd) is not always zero. in order to make it reasonably close to zero, the settings of r s and r cs are crucial. figure 33. cs pin characteristic when i l = 0 i s(zcd) v s(zcd) r s > r s(zcd) r s = r s(zcd) v s operating zcd point ideal zcd point i s
ncp1601a, NCP1601B http://onsemi.com 13 based on the cs pin (pin 4) characteristics in figure 15, figure 33 is studied. when the inductor current is exactly zero (i.e., i l(zcd) = 0), the ideal zcd point in the figure is reached where r s is r s(zcd) (536 typical). considering the tolerance, the actual sense resistor r s is needed to be higher than the ideal value of r s(zcd) to ensure that zero current signal is generated when sense current is smaller than the zcd threshold (i.e., i s < i s(zcd) ). that is, r s r s(zcd) v s(zcd) i s(zcd) (eq.15) the higher value of r s makes the longer distance between the operating and ideal zcd points in figure 33. hence, r s has to be as low as possible. the best recommended value of r s is therefore the maximum of r s(zcd) which is 1 k . now that the r s is set at a particular value which is greater than r s(zcd) . from (eq.13), the operating lines in (eq.16) with different inductor currents i l of (eq.13) are studied. v s r s r cs i l (eq.16) these operating lines are added in figure 33 to formulate figure 34. when the inductor current i l is lower than i l(zcd) , the sense current i s is lower than i s(zcd) and hence the zero current signal is generated. figure 34. cs pin characteristic with different inductor current i s(zcd) v s(zcd) v s operating zcd point i s best zcd point i l = i l(zcd) i l > i l(zcd) i l = 0 it is noted in figure 34 and (eq.16) that when the (r cs i l ) term is smaller the error or distance between the lines to the line i l = 0 is smaller. therefore, the value of the current sense resistor r cs is also recommended to be as small as possible to minimize the error in the zero current detection. overcurrent protection (ocp) overcurrent protection is reached when i s is higher than i s(ocp) (200 a typical). the offset voltage of the cs pin is v s(ocp) (3.2 mv typical) in this condition. that is (eq.17) i l(ocp) r s i s(ocp) v s(ocp) r cs when overcurrent protection threshold is reached, the drive output of the device goes low. oscillator / synchronization block figure 35. oscillator / synchronization block oscillator clock s r q zero current turn on mosfet ? + 5 v/3.5 v osc delay 0 5 1 45 a 94 a & figure 36. oscillator block timing diagram time clock inductor clock latch (latch set signal) discontinuous mode critical mode (latch output) current clock edge the ncp1601 is a dcm / crm pfc controller. in order to keep the operation in dcm or crm only, the drive output cannot turn on as long as there is some inductor current flowing through the circuit. hence, the zero current signal is provided to the oscillator / synchronization block in figure 35. an input comparator monitors the osc pin (pin 5) voltage and generates a clock signal. the negative edge of the clock signal is stored in a rs latch. when zero current is detected, the rs latch will be reset and a set signal is sent to the output drive latch which turns on the mosfet in the pfc boost circuit. figure 36 illustrates a typical timing diagram of the oscillator block. oscillator mode the osc pin (pin 5) is connected to an external capacitor c osc . when the voltage of this pin is above v sync(h) (5 v typical), the pin sinks a current i odch (94 ? 45 = 49 a typical) and the external capacitor c osc discharges. when the voltage reaches v sync(l) (3.5 v typical), the pin sources a current i och (45 a typical) and the external capacitor c osc is charged. it is noted that there is a typical 300 ns propagation delay and the 3.5 v and 5 v threshold conditions are measured on 220 pf c osc capacitor. hence, the actual oscillator hysteresis is a slightly smaller. figure 37. oscillator mode timing diagram in dcm osc pin voltage osc clock clock edge drive output (dcm) 5 v 3.5 v
ncp1601a, NCP1601B http://onsemi.com 14 there is an internal capacitance c osc(int) (36 pf typical) in the oscillator pin and the oscillator frequency is to f osc(max) (405 khz typical) when the osc pin is opened. hence, the oscillator switching frequency can be formulated in (eq.18) and represented in figure 38. (eq.18) c osc 36 pf 405 khz f osc 36 pf 0 100 200 300 400 500 600 700 0 50 100 150 200 f osc , oscillator frequency (khz) c osc , oscillator capacitor (pf) figure 38. osc pin frequency setting synchronization mode the osc pin (pin 5) receives an external digital signal with level high defined to be higher than v sync(h) (5 v typical) and level low defined to be lower than v sync(l) (3.5 v typical). an internal 9 v esd zener diode is connected to the osc pin and hence the maximum synchronization voltage is 9 v. the circuit recognizes a synchronization frequency by the time difference between two falling edge instants when the synchronization signal across the 3.5 v threshold points. the actual synchronization threshold point is a slightly higher than the 3.5 v threshold point. the minimum synchronization pulse width is 500 ns. there is a typical 350 ns propagation delay from synchronization threshold point to the moment of output goes high and there is also a typical 300 ns propagation delay from the synchronization threshold point to the moment of crossing 3.5 v. hence, the output goes high apparently when the sync signal turns to 3.5 v. a timing diagram of synchronization mode is summarized in figure 39. figure 39. synchronization mode timing diagram in dcm sync signal osc clock clock edge drive output (dcm) 5 v 3.5 v v cc undervoltage lockout (uvlo) there are two uvlo options. the device typically starts to operate when the supply voltage v cc exceeds 13.75 v for ncp1601a and 10.5 v for NCP1601B. it turns off when the supply voltage v cc goes below 9 v. an 18 v internal esd zener diode is connected to the v cc pin (pin 8). hence, the operating range is 9 v to 18 v. the 4.75 v uvlo hysteresis option of the ncp1601a and 14 a low startup current make the self?supply design easier. the 1.5 v uvlo hysteresis option of NCP1601B makes it more flexible to match with the second?stage pwm controller biasing v cc supply voltage. thermal shutdown an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 140 c. the output stage is then enabled once the temperature drops below typically 95 c (i.e., 45 c hysteresis). the thermal shutdown is provided to prevent possible device failures that could result from an accidental overheating. output drive the output stage of the device is designed for direct drive of power mosfet. it is capable of up to ?500 ma and +750 ma peak drive current and has a typical rise and fall time of 53 and 32 ns with a 1.0 nf load. table 1. power factor controller test data v in (vac) p in (w) v out (v) i out (ma) pf thd (%) efficiency (%) 90 143.4 327 400 0.998 4 91.2 110 161.1 373 400 0.997 6 92.6 130 160.5 378 400 0.996 6 94.2 150 160.9 382 400 0.993 7 95.0 180 161.6 386 400 0.990 6 95.5 190 161.7 387 400 0.986 8 95.7 210 162.0 389 400 0.980 8 96.0 230 162.2 391 400 0.973 9 96.4 250 162.8 393 400 0.959 16 96.6
ncp1601a, NCP1601B http://onsemi.com 15 figure 40. 130 w power factor correction circuit mur460 450 v 68 nf 1.5 nf 220 pf 680 k 0.1 NCP1601B 390 v 560 k 3.15 a fuse spf47283900 spp11n60s5 output 680 k 2.2 k 10 k 56 1n4934 1.5 nf vcc kbp06 100 nf input 90 vac to 260 vac 1 f1 f 68 f 450 h / 4.5 a ordering information device package shipping ? ncp1601ap pdip?8 50 units / rail ncp1601apg pdip?8 (pb?free) 50 units / rail ncp1601adr2 soic?8 2500 units / tape & reel ncp1601adr2g soic?8 (pb?free) 2500 units / tape & reel NCP1601Bp pdip?8 50 units / rail NCP1601Bpg pdip?8 (pb?free) 50 units / rail NCP1601Bdr2 soic?8 2500 units / tape & reel NCP1601Bdr2g soic?8 (pb?free) 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd801 1/d.
ncp1601a, NCP1601B http://onsemi.com 16 appendix i ? summary of equations in ncp1601 boost pfc description critical mode (crm) discontinuous mode (dcm) boost converter v out v in t 1 t 2 t 2 v out v in t 1 t 2 t 2 v out v in v out t 1 t 1 t 2 v out v in v out t 1 t 1 t 2 input current averaged by filter capacitor i in i pk 2 i in t 1 t 2 t i pk 2 voltage for on time v ton v ton v control v ton t t 1 t 2 v control mosfet on?time t 1 t 1 is constant for unity pfc v control is constant for unity pfc t 1 c ramp v control i ch t 1 li pk v in ,or t 1 (t 1 + t 2 ) is constant for unity pfc v control is constant for unity pfc t 1 v out v in v out t c ramp v control i ch t 1 li pk v in ,or switching period t 1 t 2 v out v out v in c ramp v control i ch ,or t 1 t 2 v out v out v in li pk v in t 1 t 2 t t 1 c ramp v control i ch ,or t 1 t 2 v out v out v in t c ramp v control i ch minimum inductor for crm l l (crm) v out v in v out v in i pk 1 f same as crm input impedance z in 2li ch c ramp v control same as crm input power p in v ac 2 c ramp v control 2li ch same as crm output power p out p in v ac 2 c ramp v control 2li ch same as crm maximum input power when v control = 1 v p in_max v ac 2 c ramp 2li ch same as crm minimum ramp capacitor when v control = 1 v c ramp p in v ac 2 2li ch same as crm control voltage v control v ctrl 2li ch p in c ramp v ac 2 same as crm
ncp1601a, NCP1601B http://onsemi.com 17 package dimensions soic?8 d suffix case 751?07 issue ag seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155
mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint*
ncp1601a, NCP1601B http://onsemi.com 18 package dimensions pdip?8 n suffix case 626?05 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ?a? ?b? ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m ??? 10 ??? 10 n 0.76 1.01 0.030 0.040 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp1601a/d the products described herein (ncp1601a, NCP1601B), may be covered by the following u.s. patents: 6,271,735, 6,362,067, 6,970,3 65. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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